Intel CPU model-specific LBR(Legacy LBR) evolved into Architectural LBR(Arch LBR[0]), it's the replacement of legacy LBR on new platforms. The native support patches were merged into 5.9 kernel tree, and this patch series is to enable Arch LBR in vPMU so that guest can benefit from the feature. The main advantages of Arch LBR are [1]: - Faster context switching due to XSAVES support and faster reset of LBR MSRs via the new DEPTH MSR - Faster LBR read for a non-PEBS event due to XSAVES support, which lowers the overhead of the NMI handler. - Linux kernel can support the LBR features without knowing the model number of the current CPU. >From end user's point of view, the usage of Arch LBR is the same as the Legacy LBR that has been merged in the mainline. Note, in this series, we impose one restriction for guest Arch LBR: Guest can only set the same LBR record depth as host, this is due to the special behavior of MSR_ARCH_LBR_DEPTH: 1) On write to the MSR, it'll reset all Arch LBR recording MSRs to 0s. 2) XRSTORS resets all record MSRs to 0s if the saved depth mismatches MSR_ARCH_LBR_DEPTH. Enforcing the restriction keeps the KVM enabling patch simple and straightforward. The old patch series was queued in KVM/queue for a while and finally moved to below branch after Paolo's refactor. This new patch set is built on top of Paolo's work + some fixes, it's tested on legacy platform (non-ArchLBR) and SPR platform(ArchLBR capable). [0] https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf [1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@xxxxxxxxxxxxxxx/ Original patch set: https://git.kernel.org/pub/scm/virt/kvm/kvm.git/log/?h=lbr-for-weijiang Changes in this version: 1. Fixed some minor issues in the refactored patch set. 2. Added a few minor fixes due to recent vPMU code cleanup. 3. Removed Paolo's SOBs in some modified patches. 4. Rebased to queue:kvm/kvm.git Like Xu (3): perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR KVM: x86: Add XSAVE Support for Architectural LBR Paolo Bonzini (4): KVM: PMU: disable LBR handling if architectural LBR is available KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR KVM: VMX: Support passthrough of architectural LBRs KVM: x86: Refine the matching and clearing logic for supported_xss Sean Christopherson (1): KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang (7): KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list KVM: x86/vmx: Check Arch LBR config when return perf capabilities KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest KVM: x86/vmx: Flip Arch LBREn bit on guest state change KVM: x86: Add Arch LBR data MSR access interface KVM: x86/cpuid: Advertise Arch LBR feature in CPUID arch/x86/events/intel/lbr.c | 6 +- arch/x86/include/asm/kvm_host.h | 3 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 4 + arch/x86/kvm/cpuid.c | 52 +++++++++- arch/x86/kvm/vmx/capabilities.h | 8 ++ arch/x86/kvm/vmx/nested.c | 8 ++ arch/x86/kvm/vmx/pmu_intel.c | 160 +++++++++++++++++++++++++++---- arch/x86/kvm/vmx/vmx.c | 81 +++++++++++++++- arch/x86/kvm/x86.c | 27 +++++- 10 files changed, 317 insertions(+), 33 deletions(-) base-commit: 372d07084593dc7a399bf9bee815711b1fb1bcf2 -- 2.27.0
