Quoting Janosch Frank (2022-07-29 10:26:28) [...] > diff --git a/s390x/snippets/asm/snippet-pv-diag-500.S b/s390x/snippets/asm/snippet-pv-diag-500.S > index 8dd66bd9..f4d75388 100644 > --- a/s390x/snippets/asm/snippet-pv-diag-500.S > +++ b/s390x/snippets/asm/snippet-pv-diag-500.S > @@ -8,6 +8,7 @@ > * Janosch Frank <frankja@xxxxxxxxxxxxx> > */ > #include <asm/asm-offsets.h> > +#include "macros.S" > .section .text > > /* Clean and pre-load registers that are used for diag 500 */ > @@ -21,10 +22,7 @@ lghi %r3, 3 > lghi %r4, 4 > > /* Let's jump to the next label on a PGM */ > -xgr %r5, %r5 > -stg %r5, GEN_LC_PGM_NEW_PSW So previously the PSW mask was zero and hence we had 24-bit addressing, no? Now, we have bits 31 and 32 one and hence 64 bit addressing. I guess 24-bit addressing is not appropriate here (or at least doesn't matter too much), so I guess this is intended, isn't it?
