On Tue, Aug 02, 2022, Kai Huang wrote: > On Mon, 2022-08-01 at 14:15 +0000, Sean Christopherson wrote: > > Another thing to note is that only the value needs to be per-VM, the mask can be > > KVM-wide, i.e. "mask = SUPPRESS_VE | RWX" will work for TDX and non-TDX VMs when > > EPT is enabled. > > Yeah, but is more like VMX and TDX both *happen* to have the same mask? > Theoretically, VMX only need RWX to trigger EPT misconfiguration but doesn't > need SUPPRESS_VE. Right, SUPPRESS_VE isn't strictly necessary, but KVM already deliberately avoids bit 63 because it has meaning, e.g. SUPPRESS_VE for EPT and NX for PAE and 64-bit paging. > I don't see making mask/value both per-vm is a big issue? Yes and no. No, in the sense that it's not a big issue in terms of code. Yes, because of the connotations of having a per-VM mask. While having SUPPRESS_VE in the mask for non-TDX EPT isn't strictly necessary, it's also not strictly necessary to _not_ have it in the mask. In other words, having a per-VM mask incorrectly implies that TDX _must_ have a different mask. It's also one more piece of information that developers have to track down and account for, i.e. one more thing we can screw up. The other aspect of MMIO SPTEs are that the mask bits must not overlap the generation bits or shadow-present bit, and changing any of those bits requires careful consideration, i.e. defining the set of _allowed_ mask bits on a per-VM basis would incur significant complexity without providing meaningful benefit. As a result, it's highly unlikely that we'll ever want to opportunsitically "reclaim" bit 63 for MMIO SPTEs, so there's practically zero cost if it's included in the mask for non-TDX EPT.
