On 7/25/22 4:46 PM, Paolo Bonzini wrote:
On 7/25/22 05:34, Suravee Suthikulpanit wrote:AMD does not support APIC TSC-deadline timer mode. AVIC hardware will generate GP fault when guest kernel writes 1 to bits [18] of the APIC LVTT register (offset 0x32) to set the timer mode. (Note: bit 18 is reserved on AMD system). Therefore, always intercept and let KVM emulate the MSR accesses. Fixes: f3d7c8aa6882 ("KVM: SVM: Fix x2APIC MSRs interception") Signed-off-by: Suravee Suthikulpanit<suravee.suthikulpanit@xxxxxxx>Does this fix some kvm-unit-tests testcase?
I am not sure if we have kvm-unit-tests testcases for this. I found this when enabling tsc-deadline option in QEMU causing the vm to fail to boot.
Anyway, I queued the patch, thanks! Paolo
Thank you, Suravee
