From: Sean Christopherson <seanjc@xxxxxxxxxx>
Add a separate macro for handling 64-bit only MSRs to minimize churn and
copy+paste in a future commit that will add support for read-only bits.
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
[Rebase on top of the fix for MSR_IA32_MISC_ENABLE, do not go overboard
with macros. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
---
x86/msr.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/x86/msr.c b/x86/msr.c
index b0a5db0..bb15230 100644
--- a/x86/msr.c
+++ b/x86/msr.c
@@ -26,27 +26,27 @@ struct msr_info {
#define addr_64 0x0000123456789abcULL
#define addr_ul (unsigned long)addr_64
-#define MSR_TEST(msr, val, only64) \
- { .index = msr, .name = #msr, .value = val, .is_64bit_only = only64 }
-#define MSR_TEST_RO_BITS(msr, val, only64, ro) \
- { .index = msr, .name = #msr, .value = val, .is_64bit_only = only64, .keep = ro }
+#define MSR_TEST(msr, val, ro) \
+ { .index = msr, .name = #msr, .value = val, .is_64bit_only = false, .keep = ro }
+#define MSR_TEST_ONLY64(msr, val, ro) \
+ { .index = msr, .name = #msr, .value = val, .is_64bit_only = true, .keep = ro }
struct msr_info msr_info[] =
{
- MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234, false),
- MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, false),
- MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, false),
+ MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234, 0),
+ MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, 0),
+ MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, 0),
// reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63
// read-only: 7, 11, 12
- MSR_TEST_RO_BITS(MSR_IA32_MISC_ENABLE, 0x400c50809, false, 0x1880),
- MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, false),
- MSR_TEST(MSR_FS_BASE, addr_64, true),
- MSR_TEST(MSR_GS_BASE, addr_64, true),
- MSR_TEST(MSR_KERNEL_GS_BASE, addr_64, true),
- MSR_TEST(MSR_EFER, EFER_SCE, false),
- MSR_TEST(MSR_LSTAR, addr_64, true),
- MSR_TEST(MSR_CSTAR, addr_64, true),
- MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff, true),
+ MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c50809, 0x1880),
+ MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, 0),
+ MSR_TEST_ONLY64(MSR_FS_BASE, addr_64, 0),
+ MSR_TEST_ONLY64(MSR_GS_BASE, addr_64, 0),
+ MSR_TEST_ONLY64(MSR_KERNEL_GS_BASE, addr_64, 0),
+ MSR_TEST(MSR_EFER, EFER_SCE, 0),
+ MSR_TEST_ONLY64(MSR_LSTAR, addr_64, 0),
+ MSR_TEST_ONLY64(MSR_CSTAR, addr_64, 0),
+ MSR_TEST_ONLY64(MSR_SYSCALL_MASK, 0xffffffff, 0),
// MSR_IA32_DEBUGCTLMSR needs svm feature LBRV
// MSR_VM_HSAVE_PA only AMD host
};
--
2.31.1
