On 20/06/2022 19:00, Chao Gao wrote:
On Mon, Jun 20, 2022 at 06:02:32PM +0800, Shenming Lu wrote:
+ if (enable_ipiv)
+ tertiary_exec_controls_clearbit(vmx, TERTIARY_EXEC_IPI_VIRT);
+ }
vmx_update_msr_bitmap_x2apic(vcpu);
}
Hi, just a small question here:
It seems that we clear the TERTIARY_EXEC_IPI_VIRT bit before enabling
interception for APIC_ICR when deactivating APICv on some reason.
Is there any problem with this sequence?
Both are done before the next vCPU entry. As long as no guest code can
run between them (APICv setting takes effect in guest), this sequence
shouldn't have any problem.
OK. Thanks for reply,
Shenmimg
