On 6/16/2022 11:28 PM, Paolo Bonzini wrote:
On 6/16/22 16:18, Peter Zijlstra wrote:
On Thu, Jun 16, 2022 at 12:21:20PM +0200, Paolo Bonzini wrote:
On 6/16/22 12:12, Peter Zijlstra wrote:
Do I understand this right in that a host without X86_KERNEL_IBT
cannot
run a guest with X86_KERNEL_IBT on? That seems unfortunate, since that
was exactly what I did while developing the X86_KERNEL_IBT patches.
I'm thinking that if the hardware supports it, KVM should expose it,
irrespective of the host kernel using it.
For IBT in particular, I think all processor state is only loaded
and stored
at vmentry/vmexit (does not need XSAVES), so it should be feasible.
That would be the S_CET stuff, yeah, that's VMCS managed. The U_CET
stuff is all XSAVE though.
What matters is whether XFEATURE_MASK_USER_SUPPORTED includes
XFEATURE_CET_USER.
Small correction, XFEATURE_CET_USER belongs to
XFEATURE_MASK_SUPERVISOR_SUPPORTED, the name is misleading.
If you build with !X86_KERNEL_IBT, KVM can still rely on the FPU state
for U_CET state, and S_CET is saved/restored via the VMCS independent
of X86_KERNEL_IBT.
A fundamental question is, should KVM always honor host CET enablement
before expose the feature to guest? i.e., check X86_KERNEL_IBT and
X86_SHADOW_STACK.
Paolo
But funny thing, CPUID doesn't enumerate {U,S}_CET separately. It *does*
enumerate IBT and SS separately, but for each IBT/SS you have to
implement both U and S.
That was a problem with the first series, which only implemented support
for U_CET while advertising IBT and SS (very much including S_CET), and
still is a problem with this series because S_SS is missing while
advertised.
