On Thu, Jun 9, 2022 at 7:49 PM Like Xu <like.xu.linux@xxxxxxxxx> wrote: > RDPMC Intel Operation: > > MSCB = Most Significant Counter Bit (* Model-specific *) > IF (((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0)) and (ECX indicates a supported > counter)) > THEN > EAX := counter[31:0]; > EDX := ZeroExtend(counter[MSCB:32]); > ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *) > #GP(0); > FI; > > Therefore, we will not have a #GP if !enable_pmu for legacy or future user space > programs. I beg to differ. Continue on a bit further... #GP If an invalid performance counter index is specified. If !enable_pmu, no performance counters are supported by kvm. Hence, all performance counter indices are invalid. The only CPUs for which one might argue that userspace could reasonably assume that some PMCs are valid, in spite of CPUID.0AH:EAX[7:0]=0, are the three legacy families I mentioned previously.
