On Fri, May 20, 2022, Jon Kohler wrote:
>
> > On May 18, 2022, at 10:23 AM, Jon Kohler <jon@xxxxxxxxxxx> wrote:
> >
> >> On May 17, 2022, at 9:42 PM, Sean Christopherson <seanjc@xxxxxxxxxx> wrote:
> >>> + if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) && data == BIT(0)) {
> >>
> >> Use SPEC_CTRL_IBRS instead of open coding "BIT(0)", then a chunk of the comment
> >> goes away.
> >>
> >>> + vmx->spec_ctrl = data;
> >>> + break;
> >>> + }
> >>
> >> There's no need for a separate if statement. And the boot_cpu_has() check can
> >> be dropped, kvm_spec_ctrl_test_value() has already verified the bit is writable
> >> (unless you're worried about bit 0 being used for something else?)
>
> I was (and am) worried about misbehaving guests on pre-eIBRS systems spamming IBRS
> MSR, which we wouldn’t be able to see today. Intel’s guidance for eIBRS has long been
> set it once and be done with it, so any eIBRS aware guest should behave nicely with that.
> That limits the blast radius a bit here.
Then check the guest capabilities, not the host flag.
if (data == SPEC_CTRL_IBRS &&
(vcpu->arch.arch_capabilities & ARCH_CAP_IBRS_ALL))
> Sent out the v2 just now with a few minor tweaks, only notable one was keeping
> the boot cpu check and small tweaks to comments here and there to suit.
In the future, give reviewers a bit of time to respond to a contented point before
sending out the next revision, e.g. you could have avoided v3 :-)
