On Wed, May 11, 2022 at 10:55 AM Sean Christopherson <seanjc@xxxxxxxxxx> wrote:
>
> On Tue, Apr 12, 2022, Jue Wang wrote:
> > This feature is only enabled when the vCPU has opted in to enable
> > MCG_CMCI_P.
>
> Again, waaaay too terse. What is CMCI? What does "support" mean since an astute
> reader will notice that it's impossible for MCG_CMCI_P to be set. How/when will
> the vCPU (which is wrong no? doesn't userspace do the write?) be able to opt-in?
I am rewriting the change log for every patch in this series and will
send an updated V3.
>
> > Signed-off-by: Jue Wang <juew@xxxxxxxxxx>
> > ---
> > arch/x86/kvm/lapic.c | 33 ++++++++++++++++++++++++++-------
> > arch/x86/kvm/lapic.h | 7 ++++++-
> > 2 files changed, 32 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> > index 2c770e4c0e6c..0b370ccd11a1 100644
> > --- a/arch/x86/kvm/lapic.c
> > +++ b/arch/x86/kvm/lapic.c
> > @@ -27,6 +27,7 @@
> > #include <linux/math64.h>
> > #include <linux/slab.h>
> > #include <asm/processor.h>
> > +#include <asm/mce.h>
> > #include <asm/msr.h>
> > #include <asm/page.h>
> > #include <asm/current.h>
> > @@ -364,9 +365,14 @@ static inline int apic_lvt_nmi_mode(u32 lvt_val)
> > return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
> > }
> >
> > +static inline bool kvm_is_cmci_supported(struct kvm_vcpu *vcpu)
> > +{
> > + return vcpu->arch.mcg_cap & MCG_CMCI_P;
> > +}
> > +
> > static inline int kvm_apic_get_nr_lvt_entries(struct kvm_vcpu *vcpu)
>
> I think it makes sense to take @apic here, not @vcpu, since this is an APIC-specific
> helper. kvm_apic_set_version() will need to be modified to not call
> kvm_apic_get_nr_lvt_entries() until after it has verified the local APIC is in-kernel,
> but IMO that's a good thing.
Ack.
>
> > {
> > - return KVM_APIC_MAX_NR_LVT_ENTRIES;
> > + return KVM_APIC_MAX_NR_LVT_ENTRIES - !kvm_is_cmci_supported(vcpu);
> > }
> >
> > void kvm_apic_set_version(struct kvm_vcpu *vcpu)
