From: Wanpeng Li <wanpengli@xxxxxxxxxxx> The timer is disarmed when switching between TSC deadline and other modes, however, the pending timer is still in-flight, so let's accurately set everything to a disarmed state. Fixes: 4427593258 (KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch) Signed-off-by: Wanpeng Li <wanpengli@xxxxxxxxxxx> --- arch/x86/kvm/lapic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 66b0eb0bda94..0274d17d91c2 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1562,6 +1562,7 @@ static void apic_update_lvtt(struct kvm_lapic *apic) kvm_lapic_set_reg(apic, APIC_TMICT, 0); apic->lapic_timer.period = 0; apic->lapic_timer.tscdeadline = 0; + atomic_set(&apic->lapic_timer.pending, 0); } apic->lapic_timer.timer_mode = timer_mode; limit_periodic_timer_frequency(apic); -- 2.25.1
