On Wed, 2022-05-04 at 02:31 -0500, Suravee Suthikulpanit wrote:
> When enabling x2APIC virtualization (x2AVIC), the interception of
> x2APIC MSRs must be disabled to let the hardware virtualize guest
> MSR accesses.
>
> Current implementation keeps track of list of MSR interception state
> in the svm_direct_access_msrs array. Therefore, extends the array to
> include x2APIC MSRs.
>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
> ---
> arch/x86/kvm/svm/svm.c | 25 +++++++++++++++++++++++++
> arch/x86/kvm/svm/svm.h | 4 ++--
> 2 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index 74e6f86f5dc3..314628b6bff4 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -100,6 +100,31 @@ static const struct svm_direct_access_msrs {
> { .index = MSR_IA32_CR_PAT, .always = false },
> { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
> { .index = MSR_TSC_AUX, .always = false },
> + { .index = (APIC_BASE_MSR + APIC_ID), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LVR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_TASKPRI), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_ARBPRI), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_PROCPRI), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_EOI), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_RRR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LDR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_DFR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_SPIV), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_ISR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_TMR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_IRR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_ESR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_ICR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_ICR2), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LVTT), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LVTTHMR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LVTPC), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LVT0), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LVT1), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_LVTERR), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_TMICT), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_TMCCT), .always = false },
> + { .index = (APIC_BASE_MSR + APIC_TDCR), .always = false },
> { .index = MSR_INVALID, .always = false },
> };
>
> diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h
> index 678fc7757fe4..5ed958863b81 100644
> --- a/arch/x86/kvm/svm/svm.h
> +++ b/arch/x86/kvm/svm/svm.h
> @@ -29,8 +29,8 @@
> #define IOPM_SIZE PAGE_SIZE * 3
> #define MSRPM_SIZE PAGE_SIZE * 2
>
> -#define MAX_DIRECT_ACCESS_MSRS 21
> -#define MSRPM_OFFSETS 16
> +#define MAX_DIRECT_ACCESS_MSRS 46
> +#define MSRPM_OFFSETS 32
> extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
> extern bool npt_enabled;
> extern int vgif;
Looks good.
Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx>
Best regards,
Maxim Levitsky
