On Tue, Apr 19, 2022, Maxim Levitsky wrote: > On Mon, 2022-04-18 at 15:35 +0000, Sean Christopherson wrote: > > On Mon, Apr 18, 2022, Maxim Levitsky wrote: > > > On Sat, 2022-04-16 at 03:42 +0000, Sean Christopherson wrote: > > > When L2 uses APICv/AVIC, we just safely passthrough its usage to the real hardware. > > > > > > If we were to to need to inhibit it, we would have to emulate APICv/AVIC so that L1 would > > > still think that it can use it - thankfully there is no need for that. > > > > What if L1 passes through IRQs and all MSRs to L2? ... > - vmcs02 can't have APICv enabled, because passthrough of interrupts thankfully > conflicts with APICv (virtual interrupt delivery depends on intercepting interrupts) > and even if that was false, it would have contained L2's APICv settings which should > continue to work as usual. Ah, this was the critical piece I was forgetting. I'll tweak the changelog and post a new version. Thanks!
