On 3/4/22 20:48, isaku.yamahata@xxxxxxxxx wrote:
From: Isaku Yamahata <isaku.yamahata@xxxxxxxxx>
TDX requires TDX SEAMCALL to operate Secure EPT instead of direct memory
access and TDX SEAMCALL is heavy operation. Fast page fault on private GPA
doesn't make sense. Disallow fast page fault on private GPA.
Signed-off-by: Isaku Yamahata <isaku.yamahata@xxxxxxxxx>
---
arch/x86/kvm/mmu/mmu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index e9212394a530..d8c1505155b0 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -3185,6 +3185,13 @@ static int fast_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
u64 *sptep = NULL;
uint retry_count = 0;
+ /*
+ * TDX private mapping doesn't support fast page fault because the EPT
+ * entry needs TDX SEAMCALL. not direct memory access.
"the EPT entry is read/written with TDX SEAMCALLs instead of direct
memory access".
Reviewed-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
+ */
+ if (kvm_is_private_gpa(vcpu->kvm, fault->addr))
+ return ret;
+
if (!page_fault_can_be_fast(fault))
return ret;
