Since revision IHI0069G of the GICv3 spec, an implementation is
allowed to implement MMIO-based LPI invalidation, without having to
support RVPEI (which is essentially a GICv4.1 feature).
This has the potential to make workloads using heavy LPI invalidation
fare a bit better, as they don't need to lock the access to the
command queue.
Similarly, an implementation can now expose that it allows LPIs to be
turned off, something that we always supported.
This series implements both these features, exposing the new
GICR_{INVLPIR,INVALLR,SYNCR} registers, transitions of the
GICR_CTLR.RWP bit on LPI disabling, and finally exposes these to
userspace and the guest with a new GICD_IIDR revision (and the ability
to save/restore it).
This series has been extremely useful to debug related GIC features,
and will be complemented by a few GIC driver patches.
* From v1 [1]:
- Fixed CES and IR bit numbers (shrug...)
- Plenty of small fixes all over the shop thanks to Oliver
- Rebased on top of 5.18-rc1
[1] https://lore.kernel.org/r/20220314164044.772709-1-maz@xxxxxxxxxx
Marc Zyngier (4):
irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES}
KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs
KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation
KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR,CES} as a new GICD_IIDR
revision
arch/arm64/kvm/vgic/vgic-init.c | 7 +-
arch/arm64/kvm/vgic/vgic-its.c | 64 ++++++++++-----
arch/arm64/kvm/vgic/vgic-mmio-v2.c | 18 ++++-
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 125 ++++++++++++++++++++++++++---
arch/arm64/kvm/vgic/vgic.h | 10 +++
include/kvm/arm_vgic.h | 8 +-
include/linux/irqchip/arm-gic-v3.h | 2 +
7 files changed, 195 insertions(+), 39 deletions(-)
--
2.34.1
