On Thu, Mar 31, 2022 at 6:08 PM Oliver Upton <oupton@xxxxxxxxxx> wrote: > > KVM currently does not trap ID register accesses from an AArch32 EL1. > This is painful for a couple of reasons. Certain unimplemented features > are visible to AArch32 EL1, as we limit PMU to version 3 and the debug > architecture to v8.0. Additionally, we attempt to paper over > heterogeneous systems by using register values that are safe > system-wide. All this hard work is completely sidestepped because KVM > does not set TID3 for AArch32 guests. > > Fix up handling of CP15 feature registers by simply rerouting to their > AArch64 aliases. Punt setting HCR_EL2.TID3 to a later change, as we need > to fix up the oddball CP10 feature registers still. > > Signed-off-by: Oliver Upton <oupton@xxxxxxxxxx> Reviewed-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
