Hi Jingyi, On Thu, 17 Mar 2022 07:27:45 +0000, Jingyi Wang <wangjingyi11@xxxxxxxxxx> wrote: > > Hi Marc， > > The patch "KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty > bit"(57e3cebd022fbc035dcf190ac789fd2ffc747f5b) remove the polling of > GICR_VPENDBASER.Dirty bit in vcpu_load() , while check the VPT parsing > ready in kvm_vgic_flush_hwstate() for better performance. > > Most time it works, but we have met an error on our hardware recently. > In preemptable kernel, the vcpu can be preempted between vcpu_load and > kvm_vgic_flush_hwstate. As a result, it get de-scheduled and > its_clear_vpend_valid() is called > > val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER); > val &= ~GICR_VPENDBASER_Valid; > val &= ~clr; > val |= set; > gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); > > > The function clears Valid bit meanwhile GICR_VPENDBASER_Dirty > maybe still 1, which cause the subsequent GICR_VPENDBASER_Dirty polling > fail and report ""ITS virtual pending table not cleaning". > > We have communicated with Martin from ARM and get the conclusion > that we should not change valid bit while the dirty bit not clear—— > "The dirty bit reports whether the last schedule /de-schedule > operation has completed.The restriction on not changing Valid when Dirty > is 1, is so that hardware can always complete the last operation for > starting the next". Indeed, the spec is crystal clear about that, and clearing Valid while Dirty is set is plain wrong. > > I think maybe we can check dirty bit clear before clearing the valid bit > in its_clear_vpend_valid() code. Hope to know your opinion about this > issue. Yes, that's what should happen. I came up with the patch below. Please give it a shot and let me know if that helps. If it does, I'll queue it as a fix. Thanks, M.
