Re: [PATCH] KVM: x86/svm: Clear reserved bits written to PerfEvtSeln MSRs

[Like Xu <like.xu.linux@xxxxxxxxx>]

Reviewed-by: Like Xu <likexu@xxxxxxxxxxx>

We may need this for legacy guests w/o df51fe7ea1c1, please note the
proposed changes to the (AMD architecturally defined)  #GP behavior
for AMD reserved bits without qualification.

On 27/2/2022 12:54 pm, David Dunn wrote:
> Reviewed-by: David Dunn <daviddunn@xxxxxxxxxx>
>
> On Sat, Feb 26, 2022 at 3:41 PM Jim Mattson <jmattson@xxxxxxxxxx> wrote:
>
> > +               data &= ~pmu->reserved_bits;
> > +               if (data != pmc->eventsel)
> >                          reprogram_gp_counter(pmc, data);
> > +               return 0;