According to TDX Module V0.931 Table 18.2: MSR Virtualization:
1. MSR_IA32_MISC_ENABLE is reading native and #VE in writing.
2. MSR_CSTAR is #VE in reading/writing.
MSR_CSTAR simulation is also not supported in TDX host side.
That means changing those MSRs are unsupported. So bypass related
sub-test.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@xxxxxxxxx>
Reviewed-by: Yu Zhang <yu.c.zhang@xxxxxxxxx>
---
x86/msr.c | 6 ++++++
x86/syscall.c | 3 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/x86/msr.c b/x86/msr.c
index 44fbb3b233e9..3a538c9ba693 100644
--- a/x86/msr.c
+++ b/x86/msr.c
@@ -4,6 +4,7 @@
#include "processor.h"
#include "msr.h"
#include <stdlib.h>
+#include "tdx.h"
/**
* This test allows two modes:
@@ -89,6 +90,11 @@ static void test_rdmsr_fault(struct msr_info *msr)
static void test_msr(struct msr_info *msr, bool is_64bit_host)
{
+ /* Changing MSR_IA32_MISC_ENABLE and MSR_CSTAR is unsupported in TDX */
+ if ((msr->index == MSR_IA32_MISC_ENABLE || msr->index == MSR_CSTAR) &&
+ is_tdx_guest())
+ return;
+
if (is_64bit_host || !msr->is_64bit_only) {
test_msr_rw(msr, msr->value);
diff --git a/x86/syscall.c b/x86/syscall.c
index b0df07200f50..270dfdfcce19 100644
--- a/x86/syscall.c
+++ b/x86/syscall.c
@@ -5,6 +5,7 @@
#include "msr.h"
#include "desc.h"
#include "fwcfg.h"
+#include "tdx.h"
static void test_syscall_lazy_load(void)
{
@@ -106,7 +107,7 @@ int main(int ac, char **av)
{
test_syscall_lazy_load();
- if (!no_test_device || !is_intel())
+ if ((!no_test_device || !is_intel()) && !is_tdx_guest())
test_syscall_tf();
else
report_skip("syscall TF handling");
--
2.25.1
