On Wed, Feb 23, 2022 at 01:38:03PM +0100, Borislav Petkov wrote: > On Wed, Feb 23, 2022 at 03:25:08PM +0300, Kirill A. Shutemov wrote: > > So far it is only success or failure. I used int and -EIO as failure. > > bool is enough, but I don't see a reason not to use int. > > bool it is. > > --- > From 8855bca859d8768ac04bfcf5b4aeb9cf3c69295a Mon Sep 17 00:00:00 2001 > From: Brijesh Singh <brijesh.singh@xxxxxxx> > Date: Tue, 22 Feb 2022 22:35:28 -0600 > Subject: [PATCH] x86/mm/cpa: Generalize __set_memory_enc_pgtable() > > The kernel provides infrastructure to set or clear the encryption mask > from the pages for AMD SEV, but TDX requires few tweaks. > > - TDX and SEV have different requirements to the cache and TLB > flushing. > > - TDX has own routine to notify VMM about page encryption status change. > > Modify __set_memory_enc_pgtable() and make it flexible enough to cover > both AMD SEV and Intel TDX. The AMD-specific behavior is isolated in > callback under x86_platform_cc. TDX will provide own version of the "under x86_platform.guest" > callbacks. > > [ bp: Beat into submission. ] > > Signed-off-by: Brijesh Singh <brijesh.singh@xxxxxxx> > Signed-off-by: Borislav Petkov <bp@xxxxxxx> > Link: https://lore.kernel.org/r/20220223043528.2093214-1-brijesh.singh@xxxxxxx Otherwise, LGTM: Acked-by: Kirill A. Shutemov <kirill.shutemov@xxxxxxxxxxxxxxx> -- Kirill A. Shutemov
