On 16-Feb-22 1:14 PM, Like Xu wrote:
> On 14/2/2022 6:14 pm, Ravi Bangoria wrote:
>>
>>
>> On 11-Feb-22 11:46 PM, Jim Mattson wrote:
>>> On Fri, Feb 11, 2022 at 1:56 AM Ravi Bangoria <ravi.bangoria@xxxxxxx> wrote:
>>>>
>>>>
>>>>
>>>> On 10-Feb-22 4:58 PM, Like Xu wrote:
>>>>> cc Kim and Ravi to help confirm more details about this change.
>>>>>
>>>>> On 10/2/2022 3:30 am, Jim Mattson wrote:
>>>>>> By the way, the following events from amd_event_mapping[] are not
>>>>>> listed in the Milan PPR:
>>>>>> { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES }
>>>>>> { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES }
>>>>>> { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND }
>>>>>> { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND }
>>>>>>
>>>>>> Perhaps we should build a table based on amd_f17h_perfmon_event_map[]
>>>>>> for newer AMD processors?
>
> So do we need another amd_f19h_perfmon_event_map[] in the host perf code ?
I don't think so.
CACHE_REFERENCES/MISSES eventcode and umask for Milan is same as f17h.
Although STALLED_CYCLES_FRONTEND/BACKEND has been removed from PPR
event list, it will continue to work on Milan.
Ravi
