Architectural LBR (Arch LBR) is the enhancement for previous non-Architectural LBR (Legacy LBR). This feature is introduced in Intel Architecture Instruction Set Extensions and Future Features Programming Reference[0]. The advantages of Arch LBR can be referred to in native patch series[1]. Since Arch LBR relies on XSAVES/XRSTORS to boost memory save/ restore, QEMU needs to enable the support for XSS first. Similar as Legacy LBR, QEMU uses lbr-fmt=0x3f parameter to advertise Arch LBR feature to guest. Note, the depth MSR has following side-effects: 1)On write to the MSR, it'll reset all Arch LBR recording MSRs to 0s. 2) XRSTORS resets all record MSRs to 0s if the saved depth mismatches MSR_ARCH_LBR_DEPTH. As the first step, the Arch LBR virtulization solution only supports guest depth == host depth to simplify the implementation. During live migration, before put Arch LBR msrs, it'll check the depth setting of destination host, the LBR records are written to destination only if both source and destination host depth MSR settings match. This patch series should be built with AMX QEMU patches in order to set proper xsave area size. [0]https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf [1]https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@xxxxxxxxxxxxxxx/ QEMU base-commit: ad38520bde patch 1~2: The support patches for legacy LBR. patch 3: Add a helper function to clean up code and it'll be used by Arch LBR patch too. patch 4~5: Enable XSAVES support for Arch LBR. patch 6~7: Enable Arch LBR live migration support. patch 8: Advertise Arch LBR feature. Yang Weijiang (8): qdev-properties: Add a new macro with bitmask check for uint64_t property target/i386: Add lbr-fmt vPMU option to support guest LBR target/i386: Add kvm_get_one_msr helper target/i386: Enable support for XSAVES based features target/i386: Add XSAVES support for Arch LBR target/i386: Add MSR access interface for Arch LBR target/i386: Enable Arch LBR migration states in vmstate target/i386: Support Arch LBR in CPUID enumeration hw/core/qdev-properties.c | 19 ++++ include/hw/qdev-properties.h | 12 +++ target/i386/cpu.c | 169 +++++++++++++++++++++++++++++------ target/i386/cpu.h | 56 +++++++++++- target/i386/kvm/kvm.c | 115 +++++++++++++++++++----- target/i386/machine.c | 38 ++++++++ 6 files changed, 361 insertions(+), 48 deletions(-) -- 2.27.0
