This patch adds id_reg_info for ID_DFR0_EL1 to make it writable
by userspace.
Return an error if userspace tries to set PerfMon field of the
register to a value that conflicts with the PMU configuration.
Signed-off-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
---
arch/arm64/kvm/sys_regs.c | 55 ++++++++++++++++++++++++++++++++-------
1 file changed, 45 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index ae379755fa26..90e6a85d4e31 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -633,6 +633,27 @@ static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
return 0;
}
+static int validate_id_dfr0_el1(struct kvm_vcpu *vcpu,
+ const struct id_reg_info *id_reg, u64 val)
+{
+ bool vcpu_pmu, dfr0_pmu;
+ unsigned int perfmon;
+
+ perfmon = cpuid_feature_extract_unsigned_field(val, ID_DFR0_PERFMON_SHIFT);
+ if (perfmon == 1 || perfmon == 2)
+ /* PMUv1 or PMUv2 is not allowed on ARMv8. */
+ return -EINVAL;
+
+ vcpu_pmu = kvm_vcpu_has_pmu(vcpu);
+ dfr0_pmu = id_reg_has_pmu(val, ID_DFR0_PERFMON_SHIFT, ID_DFR0_PERFMON_8_0);
+
+ /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */
+ if (vcpu_pmu ^ dfr0_pmu)
+ return -EPERM;
+
+ return 0;
+}
+
static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
{
u64 limit = id_reg->vcpu_limit_val;
@@ -693,8 +714,17 @@ static void init_id_aa64dfr0_el1_info(struct id_reg_info *id_reg)
id_reg->vcpu_limit_val = limit;
}
+static void init_id_dfr0_el1_info(struct id_reg_info *id_reg)
+{
+ /* Limit guests to PMUv3 for ARMv8.4 */
+ id_reg->vcpu_limit_val =
+ cpuid_feature_cap_perfmon_field(id_reg->vcpu_limit_val,
+ ID_DFR0_PERFMON_SHIFT,
+ ID_DFR0_PERFMON_8_4);
+}
+
static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu,
- const struct id_reg_info *idr)
+ const struct id_reg_info *idr)
{
return vcpu_has_sve(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
}
@@ -717,6 +747,12 @@ static u64 vcpu_mask_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu,
return kvm_vcpu_has_pmu(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER);
}
+static u64 vcpu_mask_id_dfr0_el1(const struct kvm_vcpu *vcpu,
+ const struct id_reg_info *idr)
+{
+ return kvm_vcpu_has_pmu(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_DFR0_PERFMON);
+}
+
static struct id_reg_info id_aa64pfr0_el1_info = {
.sys_reg = SYS_ID_AA64PFR0_EL1,
.ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR0_GIC),
@@ -773,6 +809,13 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
.vcpu_mask = vcpu_mask_id_aa64dfr0_el1,
};
+static struct id_reg_info id_dfr0_el1_info = {
+ .sys_reg = SYS_ID_DFR0_EL1,
+ .init = init_id_dfr0_el1_info,
+ .validate = validate_id_dfr0_el1,
+ .vcpu_mask = vcpu_mask_id_dfr0_el1,
+};
+
/*
* An ID register that needs special handling to control the value for the
* guest must have its own id_reg_info in id_reg_info_table.
@@ -782,6 +825,7 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
*/
#define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)])
static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = {
+ [IDREG_IDX(SYS_ID_DFR0_EL1)] = &id_dfr0_el1_info,
[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info,
[IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info,
[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] = &id_aa64dfr0_el1_info,
@@ -1712,15 +1756,6 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
/* Clear fields for opt-in features that are not configured. */
val &= ~(id_reg->vcpu_mask(vcpu, id_reg));
- switch (id) {
- case SYS_ID_DFR0_EL1:
- /* Limit guests to PMUv3 for ARMv8.4 */
- val = cpuid_feature_cap_perfmon_field(val,
- ID_DFR0_PERFMON_SHIFT,
- kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
- break;
- }
-
return val;
}
--
2.35.1.265.g69c8d7142f-goog
