Hi Marc,
On Fri, Jan 28, 2022 at 12:18:33PM +0000, Marc Zyngier wrote:
> From: Jintack Lim <jintack.lim@xxxxxxxxxx>
>
> Forward the EL1 virtual memory register traps to the virtual EL2 if they
> are not coming from the virtual EL2 and the virtual HCR_EL2.TVM or TRVM
> bit is set.
>
> This is for recursive nested virtualization.
>
> Signed-off-by: Jintack Lim <jintack.lim@xxxxxxxxxx>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> ---
> arch/arm64/kvm/sys_regs.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index ccd063d6cb69..edaf287c7ec9 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -351,6 +351,13 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu,
> if (el12_reg(p) && forward_nv_traps(vcpu))
> return false;
>
> + if (!el12_reg(p)) {
> + u64 bit = p->is_write ? HCR_TVM : HCR_TRVM;
> +
> + if (forward_traps(vcpu, bit))
> + return false;
This part of the TVM bit description from the architecture manual (page
D13-3290) got me really stumped for a while:
"When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes
other than a direct read of this field".
But I soon realized it's forbidden by the architecture to eret to EL1 when TGE
is set, so all's good. I wonder why that part was added to the TVM bit
description though.
Regardless, the patch looks good to me:
Reviewed-by: Alexandru Elisei <alexandru.elisei@xxxxxxx>
Thanks,
Alex
> + }
> +
> /* We don't expect TRVM on the host */
> BUG_ON(!vcpu_is_el2(vcpu) && !p->is_write);
>
> --
> 2.30.2
>
