Perf counter may overcount for a list of Retire Based Events. Implement
workaround for Zen3 Family 19 Model 00-0F processors as suggested in
Revision Guide[1]:
To count the non-FP affected PMC events correctly:
o Use Core::X86::Msr::PERF_CTL2 to count the events, and
o Program Core::X86::Msr::PERF_CTL2[43] to 1b, and
o Program Core::X86::Msr::PERF_CTL2[20] to 0b.
Note that the specified workaround applies only to counting events and
not to sampling events. Thus sampling event will continue functioning
as is.
Although the issue exists on all previous Zen revisions, the workaround
is different and thus not included in this patch.
This patch needs Like's patch[2] to make it work on kvm guest.
[1] https://bugzilla.kernel.org/attachment.cgi?id=298241
[2] https://lore.kernel.org/lkml/20220117055703.52020-1-likexu@xxxxxxxxxxx
Signed-off-by: Ravi Bangoria <ravi.bangoria@xxxxxxx>
---
v1: https://lore.kernel.org/r/20220202042838.6532-1-ravi.bangoria@xxxxxxx
v1->v2:
- Don't put any constraint on sampling events
- s/errata/erratum/
arch/x86/events/amd/core.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 9687a8aef01c..d4dc5ff35366 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -874,6 +874,24 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, int idx,
}
}
+/* Overcounting of Retire Based Events Erratum */
+static struct event_constraint retire_event_constraints[] __read_mostly = {
+ EVENT_CONSTRAINT(0xC0, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xC1, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xC2, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xC3, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xC4, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xC5, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xC8, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xC9, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xCA, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xCC, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0xD1, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0x1000000C7, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT(0x1000000D0, 0x4, AMD64_EVENTSEL_EVENT),
+ EVENT_CONSTRAINT_END
+};
+
static struct event_constraint pair_constraint;
static struct event_constraint *
@@ -881,10 +899,30 @@ amd_get_event_constraints_f17h(struct cpu_hw_events *cpuc, int idx,
struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
+ struct event_constraint *c;
if (amd_is_pair_event_code(hwc))
return &pair_constraint;
+ /*
+ * Although 'Overcounting of Retire Based Events' erratum exists
+ * for older generation cpus, workaround to set bit 43 works only
+ * for Family 19h Model 00-0Fh as per the Revision Guide.
+ */
+ if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model <= 0xf) {
+ if (is_sampling_event(event))
+ goto out;
+
+ for_each_event_constraint(c, retire_event_constraints) {
+ if (constraint_match(c, event->hw.config)) {
+ event->hw.config |= (1ULL << 43);
+ event->hw.config &= ~(1ULL << 20);
+ return c;
+ }
+ }
+ }
+
+out:
return &unconstrained;
}
--
2.27.0
