If APIC IDs are not sequential (e.g., 0, 1, 2, 3), then hard-coding the
CPU indexes will break sending IRQs to correct CPUs.
Fixes: b2a1ee7ea179 ("x86: ioapic: Test physical and logical destination mode")From c5c23c8761db990fa25f5adb4c13a6c760e4c0f7 Mon Sep 17 00:00:00 2001
From: Metin Kaya <metikaya@xxxxxxxxxx>
Date: Mon, 24 Jan 2022 11:38:38 +0000
Subject: [PATCH 3/3] x86/ioapic: use APIC ID map instead of hard-coded CPU
index
If APIC IDs are not sequential (e.g., 0, 1, 2, 3), then hard-coding the
CPU indexes will break sending IRQs to correct CPUs.
Fixes: b2a1ee7ea179 ("x86: ioapic: Test physical and logical destination mode")
Signed-off-by: Metin Kaya <metikaya@xxxxxxxxxx>
---
x86/ioapic.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/x86/ioapic.c b/x86/ioapic.c
index 0adf323..0d37b37 100644
--- a/x86/ioapic.c
+++ b/x86/ioapic.c
@@ -423,7 +423,7 @@ static void test_ioapic_physical_destination_mode(void)
.vector = 0x85,
.delivery_mode = 0,
.dest_mode = 0,
- .dest_id = 0x1,
+ .dest_id = id_map[1],
.trig_mode = TRIGGER_LEVEL,
};
handle_irq(0x85, ioapic_isr_85);
@@ -451,11 +451,14 @@ static void test_ioapic_logical_destination_mode(void)
{
/* Number of vcpus which are configured/set in dest_id */
int nr_vcpus = 3;
+ uint8_t dest_id = (1U << id_map[0]) |
+ (1U << id_map[2]) |
+ (1U << id_map[3]);
ioapic_redir_entry_t e = {
.vector = 0x86,
.delivery_mode = 0,
.dest_mode = 1,
- .dest_id = 0xd,
+ .dest_id = dest_id,
.trig_mode = TRIGGER_LEVEL,
};
handle_irq(0x86, ioapic_isr_86);
--
2.32.0
