>From AMD erratum 1292: The processor may experience sampling inaccuracies that cause the following performance counters to overcount retire-based events. • PMCx0C0 [Retired Instructions] • PMCx0C1 [Retired Uops] • PMCx0C2 [Retired Branch Instructions] • PMCx0C3 [Retired Branch Instructions Mispredicted] • PMCx0C4 [Retired Taken Branch Instructions] • PMCx0C5 [Retired Taken Branch Instructions Mispredicted] • PMCx0C8 [Retired Near Returns] • PMCx0C9 [Retired Near Returns Mispredicted] • PMCx0CA [Retired Indirect Branch Instructions Mispredicted] • PMCx0CC [Retired Indirect Branch Instructions] • PMCx0D1 [Retired Conditional Branch Instructions] • PMCx1C7 [Retired Mispredicted Branch Instructions due to Direction Mismatch] • PMCx1D0 [Retired Fused Branch Instructions] The recommended workaround is: To count the non-FP affected PMC events correctly: • Use Core::X86::Msr::PERF_CTL2 to count the events, and • Program Core::X86::Msr::PERF_CTL2[43] to 1b, and • Program Core::X86::Msr::PERF_CTL2[20] to 0b. It's unfortunate that kvm's PMU virtualization completely circumvents any attempt to employ the recommended workaround. Admittedly, bit 43 is "reserved," and it would be foolish for a hypervisor to let a guest set a reserved bit in a host MSR. But, even the first recommendation is impossible under KVM, because the host's perf subsystem actually decides which hardware counter is going to be used, regardless of what the guest asks for. Am I the only one bothered by this?
