On 11/1/2022 3:59 pm, Xiaoyao Li wrote:
+#define GUEST_SUPPORTED_CPUID_14_EBX \
+ (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
+
+#define GUEST_SUPPORTED_CPUID_14_ECX \
+ (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(31))
+
I doubt BIT(3) of CPUID_14_ECX can be exposed to guest directly.
It means "output to Trace Transport Subsystem Supported". If I understand
correctly, it at least needs passthrough of the said Transport Subsystem or
emulation of it.
I'm not surprised that we can route Intel Guest PT output to a platform-specific
trace endpoint (e.g., physical or emulated JTAG) as an MMIO debug port.
