On Fri, 2021-12-17 at 19:11 +0000, David Woodhouse wrote: > I note that one is in native_write_msr() though. I wonder what it's > writing? CPU Reset (CPU 0) RAX=0000000000000000 RBX=0000000000000202 RCX=0000000000000828 RDX=0000000000000000 RSI=0000000000000000 RDI=0000000000000828 RBP=0000000000000000 RSP=ffffc90000023ce0 R8 =0000000000000000 R9 =ffffc90000023b60 R10=0000000000000001 R11=0000000000000001 R12=000000000000069a R13=0000000000000005 R14=000000000000001c R15=0000000000000001 RIP=ffffffff810705c6 RFL=00000206 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 It's writing zero (%rax/%rsi) to MSR 0x828 (%rcx/%rdi) which is the X2APIC's APIC_ESR. Can you reproduce this without the guest being in X2APIC mode? You'll have to cut it back to only 254 vCPUs for that test.
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