According to section "System-Control Registers" in APM vol 2,
"All CR3 bits are writable, except for unimplemented physical
address bits, which must be cleared to 0."
Therefore, generate the MBZ mask for CR3 base on the the VCPU's implemented
physical bit width, instead of using a fixed MBZ mask.
Signed-off-by: Krish Sadhukhan <krish.sadhkhan@xxxxxxxxxx>
---
x86/svm.h | 1 -
x86/svm_tests.c | 7 ++++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/x86/svm.h b/x86/svm.h
index f74b13a..cdab44a 100644
--- a/x86/svm.h
+++ b/x86/svm.h
@@ -349,7 +349,6 @@ struct __attribute__ ((__packed__)) vmcb {
#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
#define SVM_CR0_RESERVED_MASK 0xffffffff00000000U
-#define SVM_CR3_LONG_MBZ_MASK 0xfff0000000000000U
#define SVM_CR3_LONG_RESERVED_MASK 0x0000000000000fe7U
#define SVM_CR3_PAE_LEGACY_RESERVED_MASK 0x0000000000000007U
#define SVM_CR4_LEGACY_RESERVED_MASK 0xff08e000U
diff --git a/x86/svm_tests.c b/x86/svm_tests.c
index 4897a21..8a3f2e9 100644
--- a/x86/svm_tests.c
+++ b/x86/svm_tests.c
@@ -2317,11 +2317,12 @@ static void test_cr3(void)
* [63:52] - long mode
*/
u64 cr3_saved = vmcb->save.cr3;
+ u64 cr3_mbz_mask = GENMASK_ULL(63, cpuid_maxphyaddr());
- SVM_TEST_CR_RESERVED_BITS(0, 63, 1, 3, cr3_saved,
- SVM_CR3_LONG_MBZ_MASK, SVM_EXIT_ERR, "");
+ SVM_TEST_CR_RESERVED_BITS(0, 63, 1, 3, cr3_saved, cr3_mbz_mask,
+ SVM_EXIT_ERR, "");
- vmcb->save.cr3 = cr3_saved & ~SVM_CR3_LONG_MBZ_MASK;
+ vmcb->save.cr3 = cr3_saved & ~cr3_mbz_mask;
report(svm_vmrun() == SVM_EXIT_VMMCALL, "Test CR3 63:0: %lx",
vmcb->save.cr3);
--
2.27.0
