On 9/12/2021 12:25 pm, Jim Mattson wrote:
Not your change, but if the event is counting anything based on cycles, and the guest TSC is scaled to run at a different rate from the host TSC, doesn't the initial value of the underlying hardware counter have to be adjusted as well, so that the interrupt arrives when the guest's counter overflows rather than when the host's counter overflows?
I've thought about this issue too and at least the Intel Specification did not let me down on this detail: "The counter changes in the VMX non-root mode will follow VMM's use of the TSC offset or TSC scaling VMX controls" Not knowing if AMD or the real world hardware will live up to this expectation and I'm pessimistic. cc Andi and Kim.
