Hi Sumit, On 12/3/21 2:13 PM, Sumit Gupta wrote: > Hi Eric, > >> This series brings the IOMMU part of HW nested paging support >> in the SMMUv3. >> >> The SMMUv3 driver is adapted to support 2 nested stages. >> >> The IOMMU API is extended to convey the guest stage 1 >> configuration and the hook is implemented in the SMMUv3 driver. >> >> This allows the guest to own the stage 1 tables and context >> descriptors (so-called PASID table) while the host owns the >> stage 2 tables and main configuration structures (STE). >> >> This work mainly is provided for test purpose as the upper >> layer integration is under rework and bound to be based on >> /dev/iommu instead of VFIO tunneling. In this version we also get >> rid of the MSI BINDING ioctl, assuming the guest enforces >> flat mapping of host IOVAs used to bind physical MSI doorbells. >> In the current QEMU integration this is achieved by exposing >> RMRs to the guest, using Shameer's series [1]. This approach >> is RFC as the IORT spec is not really meant to do that >> (single mapping flag limitation). >> >> Best Regards >> >> Eric >> >> This series (Host) can be found at: >> https://github.com/eauger/linux/tree/v5.15-rc7-nested-v16 >> This includes a rebased VFIO integration (although not meant >> to be upstreamed) >> >> Guest kernel branch can be found at: >> https://github.com/eauger/linux/tree/shameer_rmrr_v7 >> featuring [1] >> >> QEMU integration (still based on VFIO and exposing RMRs) >> can be found at: >> https://github.com/eauger/qemu/tree/v6.1.0-rmr-v2-nested_smmuv3_v10 >> (use iommu=nested-smmuv3 ARM virt option) >> >> Guest dependency: >> [1] [PATCH v7 0/9] ACPI/IORT: Support for IORT RMR node >> >> History: >> >> v15 -> v16: >> - guest RIL must support RIL >> - additional checks in the cache invalidation hook >> - removal of the MSI BINDING ioctl (tentative replacement >> by RMRs) >> >> >> Eric Auger (9): >> iommu: Introduce attach/detach_pasid_table API >> iommu: Introduce iommu_get_nesting >> iommu/smmuv3: Allow s1 and s2 configs to coexist >> iommu/smmuv3: Get prepared for nested stage support >> iommu/smmuv3: Implement attach/detach_pasid_table >> iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs >> iommu/smmuv3: Implement cache_invalidate >> iommu/smmuv3: report additional recoverable faults >> iommu/smmuv3: Disallow nested mode in presence of HW MSI regions > Hi Eric, > > I validated the reworked test patches in v16 from the given > branches with Kernel v5.15 & Qemu v6.2. Verified them with > NVMe PCI device assigned to Guest VM. > Sorry, forgot to update earlier. > > Tested-by: Sumit Gupta <sumitg@xxxxxxxxxx> Thank you very much! Best Regards Eric > > Thanks, > Sumit Gupta >
