Hi Eric,
On Thu, Nov 25, 2021 at 7:35 AM Eric Auger <eauger@xxxxxxxxxx> wrote:
>
> Hi Reiji,
>
> On 11/17/21 7:43 AM, Reiji Watanabe wrote:
> > This patch adds id_reg_info for ID_AA64PFR0_EL1 to make it writable by
> > userspace.
> >
> > The CSV2/CSV3 fields of the register were already writable and values
> > that were written for them affected all vCPUs before. Now they only
> > affect the vCPU.
> > Return an error if userspace tries to set SVE/GIC field of the register
> > to a value that conflicts with SVE/GIC configuration for the guest.
> > SIMD/FP/SVE fields of the requested value are validated according to
> > Arm ARM.
> >
> > Signed-off-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
> > ---
> > arch/arm64/kvm/sys_regs.c | 159 ++++++++++++++++++++++++--------------
> > 1 file changed, 103 insertions(+), 56 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index 1552cd5581b7..35400869067a 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -401,6 +401,92 @@ static void id_reg_info_init(struct id_reg_info *id_reg)
> > id_reg->init(id_reg);
> > }
> >
> > +#define kvm_has_gic3(kvm) \
> > + (irqchip_in_kernel(kvm) && \
> > + (kvm)->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
> you may move this macro to kvm/arm_vgic.h as this may be used in
> vgic/vgic-v3.c too
Thank you for the suggestion. I will move that to kvm/arm_vgic.h.
> > +
> > +static int validate_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > + const struct id_reg_info *id_reg, u64 val)
> > +{
> > + int fp, simd;
> > + bool vcpu_has_sve = vcpu_has_sve(vcpu);
> > + bool pfr0_has_sve = id_aa64pfr0_sve(val);
> > + int gic;
> > +
> > + simd = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_ASIMD_SHIFT);
> > + fp = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_FP_SHIFT);
> > + if (simd != fp)
> > + return -EINVAL;
> > +
> > + /* fp must be supported when sve is supported */
> > + if (pfr0_has_sve && (fp < 0))
> > + return -EINVAL;
> > +
> > + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */
> > + if (vcpu_has_sve ^ pfr0_has_sve)
> > + return -EPERM;
> > +
> > + gic = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_GIC_SHIFT);
> > + if ((gic > 0) ^ kvm_has_gic3(vcpu->kvm))
> > + return -EPERM;
>
> Sometimes from a given architecture version, some lower values are not
> allowed. For instance from ARMv8.5 onlt 1 is permitted for CSV3.
> Shouldn't we handle that kind of check?
As far as I know, there is no way for guests to identify the
architecture revision (e.g. v8.1, v8.2, etc). It might be able
to indirectly infer the revision though (from features that are
available or etc).
> > +
> > + return 0;
> > +}
> > +
> > +static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
> > +{
> > + u64 limit = id_reg->vcpu_limit_val;
> > + unsigned int gic;
> > +
> > + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
> > + if (!system_supports_sve())
> > + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
> > +
> > + /*
> > + * The default is to expose CSV2 == 1 and CSV3 == 1 if the HW
> > + * isn't affected. Userspace can override this as long as it
> > + * doesn't promise the impossible.
> > + */
> > + limit &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2) |
> > + ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3));
> > +
> > + if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
> > + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), 1);
> > + if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED)
> > + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), 1);
> > +
> > + gic = cpuid_feature_extract_unsigned_field(limit, ID_AA64PFR0_GIC_SHIFT);
> > + if (gic > 1) {
> > + /* Limit to GICv3.0/4.0 */
> > + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
> > + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);
> > + }
> > + id_reg->vcpu_limit_val = limit;
> > +}
> > +
> > +static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> > + const struct id_reg_info *idr)
> > +{
> > + u64 val = idr->vcpu_limit_val;
> > +
> > + if (!vcpu_has_sve(vcpu))
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
> > +
> > + if (!kvm_has_gic3(vcpu->kvm))
> > + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
> > +
> > + return val;
> > +}
> > +
> > +static struct id_reg_info id_aa64pfr0_el1_info = {
> > + .sys_reg = SYS_ID_AA64PFR0_EL1,
> > + .ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) |
> > + S_FCT(ID_AA64PFR0_FP_SHIFT, FCT_LOWER_SAFE),
> is it needed as it is the default?
> > + .ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) |
> > + S_FCT(ID_AA64PFR0_FP_SHIFT, FCT_LOWER_SAFE),
> is it needed as it is the default?
They are needed because they are signed fields (the default is unsigned
and FCT_LOWER_SAFE). Having said that, ftr_check_types itself will be
gone in the next version (as arm64_ftr_bits will be used instead).
Thanks,
Reiji
