Hi Reiji,
On 11/17/21 7:43 AM, Reiji Watanabe wrote:
> This patch adds id_reg_info for ID_DFR0_EL1 to make it writable
> by userspace.
>
> Return an error if userspace tries to set PerfMon field of the
> register to a value that conflicts with the PMU configuration.
>
> Signed-off-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
> ---
> arch/arm64/kvm/sys_regs.c | 52 ++++++++++++++++++++++++++++++++++-----
> 1 file changed, 46 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 0faf458b0efb..fbd335ac5e6b 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -665,6 +665,27 @@ static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> return 0;
> }
>
> +static int validate_id_dfr0_el1(struct kvm_vcpu *vcpu,
> + const struct id_reg_info *id_reg, u64 val)
> +{
> + bool vcpu_pmu, dfr0_pmu;
> + unsigned int perfmon;
> +
> + perfmon = cpuid_feature_extract_unsigned_field(val, ID_DFR0_PERFMON_SHIFT);
> + if (perfmon == 1 || perfmon == 2)
> + /* PMUv1 or PMUv2 is not allowed on ARMv8. */
> + return -EINVAL;
> +
> + vcpu_pmu = kvm_vcpu_has_pmu(vcpu);
> + dfr0_pmu = id_reg_has_pmu(val, ID_DFR0_PERFMON_SHIFT, ID_DFR0_PERFMON_8_0);
> +
> + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */
> + if (vcpu_pmu ^ dfr0_pmu)
> + return -EPERM;
This breaks the migration on ThunderX v2 as vcpu_pmu == true and
dfr0_pmu == false
Thanks
Eric
> +
> + return 0;
> +}
> +
> static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
> {
> u64 limit = id_reg->vcpu_limit_val;
> @@ -725,6 +746,15 @@ static void init_id_aa64dfr0_el1_info(struct id_reg_info *id_reg)
> id_reg->vcpu_limit_val = limit;
> }
>
> +static void init_id_dfr0_el1_info(struct id_reg_info *id_reg)
> +{
> + /* Limit guests to PMUv3 for ARMv8.4 */
> + id_reg->vcpu_limit_val =
> + cpuid_feature_cap_perfmon_field(id_reg->vcpu_limit_val,
> + ID_DFR0_PERFMON_SHIFT,
> + ID_DFR0_PERFMON_8_4);
> +}
> +
> static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
> const struct id_reg_info *idr)
> {
> @@ -762,6 +792,14 @@ static u64 get_reset_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
> (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER)));
> }
>
> +static u64 get_reset_id_dfr0_el1(struct kvm_vcpu *vcpu,
> + const struct id_reg_info *idr)
> +{
> + return kvm_vcpu_has_pmu(vcpu) ?
> + idr->vcpu_limit_val :
> + (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_DFR0_PERFMON)));
> +}
> +
> static struct id_reg_info id_aa64pfr0_el1_info = {
> .sys_reg = SYS_ID_AA64PFR0_EL1,
> .ftr_check_types = S_FCT(ID_AA64PFR0_ASIMD_SHIFT, FCT_LOWER_SAFE) |
> @@ -814,6 +852,13 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
> .get_reset_val = get_reset_id_aa64dfr0_el1,
> };
>
> +static struct id_reg_info id_dfr0_el1_info = {
> + .sys_reg = SYS_ID_DFR0_EL1,
> + .init = init_id_dfr0_el1_info,
> + .validate = validate_id_dfr0_el1,
> + .get_reset_val = get_reset_id_dfr0_el1,
> +};
> +
> /*
> * An ID register that needs special handling to control the value for the
> * guest must have its own id_reg_info in id_reg_info_table.
> @@ -823,6 +868,7 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
> */
> #define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)])
> static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = {
> + [IDREG_IDX(SYS_ID_DFR0_EL1)] = &id_dfr0_el1_info,
> [IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info,
> [IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info,
> [IDREG_IDX(SYS_ID_AA64DFR0_EL1)] = &id_aa64dfr0_el1_info,
> @@ -1677,12 +1723,6 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
> val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), gic_lim);
> }
> break;
> - case SYS_ID_DFR0_EL1:
> - /* Limit guests to PMUv3 for ARMv8.4 */
> - val = cpuid_feature_cap_perfmon_field(val,
> - ID_DFR0_PERFMON_SHIFT,
> - kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
> - break;
> }
>
> return val;
>
