On Tue, Nov 16, 2021, Paolo Bonzini wrote: > On 11/5/21 21:03, Sean Christopherson wrote: > > But I think even that is flawed, as APICv can be dynamically deactivated and > > re-activated while the VM is running, and I don't see a path that re-updates > > the IRTE when APICv is re-activated. So I think a more conservative check is > > needed, e.g. > > > > diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c > > index 5f81ef092bd4..6cf5b2e86118 100644 > > --- a/arch/x86/kvm/vmx/posted_intr.c > > +++ b/arch/x86/kvm/vmx/posted_intr.c > > @@ -272,7 +272,7 @@ int pi_update_irte(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, > > > > if (!kvm_arch_has_assigned_device(kvm) || > > !irq_remapping_cap(IRQ_POSTING_CAP) || > > - !kvm_vcpu_apicv_active(kvm->vcpus[0])) > > + !irqchip_in_kernel(kvm) || !enable_apicv) > > return 0; > > > > idx = srcu_read_lock(&kvm->irq_srcu); > > What happens then if pi_pre_block is called and the IRTE denotes a posted > interrupt? > > I might be wrong, but it seems to me that you have to change all of the > occurrences this way. As soon as enable_apicv is set, you need to go > through the POSTED_INTR_WAKEUP_VECTOR just in case. Sorry, I didn't grok that at all. All occurences of what?
