On 13/11/2021 7:52 am, Jim Mattson wrote:
Google Cloud has a customer that needs accurate virtualization of two architected PMU events on Intel hardware: "instructions retired" and "branch instructions retired." The existing PMU virtualization code fails to account for instructions that are emulated by kvm.
Does this customer need to set force_emulation_prefix=Y ? Is this "accurate statistics" capability fatal to the use case ?
Accurately virtualizing all PMU events for all microarchitectures is a herculean task, but there are only 8 architected events, so maybe we can at least try to get those right.
I assume you mean the architectural events "Instruction Retired" and "Branch Instruction Retired" defined by the Intel CPUID since it looks we don't have a similar concept on AMD. This patch set opens Pandora's Box, especially when we have the real accurate Guest PEBS facility, and things get even more complicated for just some PMU corner use cases.
Eric Hankland wrote this code originally, but his plate is full, so I've volunteered to shepherd the changes through upstream acceptance.
Does Eric have more code to implement accurate virtualization on the following events ? "UnHalted Core Cycles" "UnHalted Reference Cycles" "LLC Reference" "LLC Misses" "Branch Misses Retired" "Topdown Slots" (unimplemented) Obviously, it's difficult, even absurd, to emulate these.
Jim Mattson (2): KVM: x86: Update vPMCs when retiring instructions KVM: x86: Update vPMCs when retiring branch instructions arch/x86/kvm/emulate.c | 57 +++++++++++++++++++++----------------- arch/x86/kvm/kvm_emulate.h | 1 + arch/x86/kvm/pmu.c | 31 +++++++++++++++++++++ arch/x86/kvm/pmu.h | 1 + arch/x86/kvm/vmx/nested.c | 6 +++- arch/x86/kvm/x86.c | 5 ++++ 6 files changed, 75 insertions(+), 26 deletions(-)
