While an IRQ is not "guaranteed to be visible until an appropriate invalidation" it doesn't stop the actual implementation delivering it earlier if it wants to. This is the case for QEMU's TCG and as tests should only be checking architectural compliance this check is invalid. Signed-off-by: Alex Bennée <alex.bennee@xxxxxxxxxx> Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx> Cc: Shashi Mallela <shashi.mallela@xxxxxxxxxx> Message-Id: <20210525172628.2088-2-alex.bennee@xxxxxxxxxx> --- v3 - reflow the comment, drop "willingly do not call" as per Eric's suggestion --- arm/gic.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 98135ef..1e3ea80 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -732,21 +732,17 @@ static void test_its_trigger(void) "dev2/eventid=20 does not trigger any LPI"); /* - * re-enable the LPI but willingly do not call invall - * so the change in config is not taken into account. - * The LPI should not hit + * re-enable the LPI. While "A change to the LPI configuration + * is not guaranteed to be visible until an appropriate + * invalidation operation has completed" hardware that doesn't + * implement caches may have delivered the event at any point + * after the enabling. Check the LPI has hit by the time the + * invall is done. */ gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT); stats_reset(); cpumask_clear(&mask); its_send_int(dev2, 20); - wait_for_interrupts(&mask); - report(check_acked(&mask, -1, -1), - "dev2/eventid=20 still does not trigger any LPI"); - - /* Now call the invall and check the LPI hits */ - stats_reset(); - cpumask_clear(&mask); cpumask_set_cpu(3, &mask); its_send_invall(col3); wait_for_interrupts(&mask); -- 2.30.2
