On Thu, 2021-10-28 at 00:09 +0200, Paolo Bonzini wrote: > On 27/10/21 18:04, Sean Christopherson wrote: > > > > + /* > > > > + * The smp_wmb() in kvm_make_request() pairs with the smp_mb_*() > > > > + * after setting vcpu->mode in vcpu_enter_guest(), thus the vCPU > > > > + * is guaranteed to see the event request if triggering a posted > > > > + * interrupt "fails" because vcpu->mode != IN_GUEST_MODE. > > > > > > What this smp_wmb() pair with, is the smp_mb__after_atomic in > > > kvm_check_request(KVM_REQ_EVENT, vcpu). > > > > I don't think that's correct. There is no kvm_check_request() in the relevant path. > > kvm_vcpu_exit_request() uses kvm_request_pending(), which is just a READ_ONCE() > > without a barrier. > > Ok, we are talking about two different set of barriers. This is mine: > > - smp_wmb() in kvm_make_request() pairs with the smp_mb__after_atomic() in > kvm_check_request(); it ensures that everything before the request > (in this case, pi_pending = true) is seen by inject_pending_event. > > - pi_test_and_set_on() orders the write to ON after the write to PIR, > pairing with vmx_sync_pir_to_irr and ensuring that the bit in the PIR is > seen. > > And this is yours: > > - pi_test_and_set_on() _also_ orders the write to ON before the read of > vcpu->mode, pairing with vcpu_enter_guest() > > - kvm_make_request() however does _not_ order the write to > vcpu->requests before the read of vcpu->mode, even though it's needed. > Usually that's handled by kvm_vcpu_exiting_guest_mode(), but in this case > vcpu->mode is read in kvm_vcpu_trigger_posted_interrupt. Yes indeed, kvm_make_request() writes the vcpu->requests after the memory barrier, and then there is no barrier until reading of vcpu->mode in kvm_vcpu_trigger_posted_interrupt. > > So vmx_deliver_nested_posted_interrupt() is missing a smp_mb__after_atomic(). > It's documentation only for x86, but still easily done in v3. > > Paolo > I used this patch as a justification to read Paolo's excellent LWN series of articles on memory barriers, to refresh my knowledge of the memory barriers and understand the above analysis better. https://lwn.net/Articles/844224/ I agree with the above, but this is something that is so easy to make a mistake that I can't be 100% sure. Best regards, Maxim Levitsky
