On Tue, 19 Oct 2021 16:23:28 -0300
Jason Gunthorpe <jgg@xxxxxxxxxx> wrote:
> On Tue, Oct 19, 2021 at 12:43:52PM -0600, Alex Williamson wrote:
> > > + /* Running switches on */
> > > + if (((old_state ^ state) & VFIO_DEVICE_STATE_RUNNING) &&
> > > + (state & VFIO_DEVICE_STATE_RUNNING)) {
> > > + ret = mlx5vf_pci_unfreeze_device(mvdev);
> > > + if (ret)
> > > + return ret;
> > > + ret = mlx5vf_pci_unquiesce_device(mvdev);
> > > + if (ret) {
> > > + vmig->vfio_dev_state = VFIO_DEVICE_STATE_ERROR;
> > > + return ret;
> > > + }
> > > + }
> >
> > Per previous discussion, I understand that freeze and quiesce are
> > loosely stop-responding-to-dma and stop-sending-dma, respectively.
> > Once we're quiesced and frozen, device state doesn't change. What are
> > the implications to userspace that we don't expose a quiesce state
> > (yet)? I'm wondering if this needs to be resolved before we introduce
> > our first in-tree user of the uAPI (and before QEMU support becomes
> > non-experimental). Thanks,
>
> The prototype patch I saw added a 4th bit to the state which was
> 1 == 'not dma initiating'
> As you suggested I think a cap bit someplace should be defined if the
> driver supports the 4th bit.
>
> Otherwise, I think it is backwards compatible, the new logic would be
> two ifs
>
> if ((flipped & STATE_NDMA) &&
> (flipped & (STATE_NDMA | STATE_RUNNING)) == STATE_NDMA | STATE_RUNNING)
> mlx5vf_pci _quiesce_device()
>
> [..]
>
> if ((flipped == (STATE_NDMA)) &&
> (flipped & (STATE_NDMA | STATE_RUNNING)) == STATE_RUNNING)
> mlx5vf_pci_unquiesce_device()
>
> Sequenced before/after the other calls to quiesce_device
>
> So if userspace doesn't use it then the same driver behavior is kept,
> as it never sees STATE_NDMA flip
>
> Asking for STATE_NDMA !STATE_RUNNING is just ignored because !RUNNING
> already implies NDMA
>
> .. and some optimization of the logic to avoid duplicated work
Ok, so this new bit just augments how the device interprets _RUNNING,
it's essentially a don't-care relative to _SAVING or _RESTORING.
I think that gives us this table:
| NDMA | RESUMING | SAVING | RUNNING |
+----------+----------+----------+----------+ ---
| X | 0 | 0 | 0 | ^
+----------+----------+----------+----------+ |
| 0 | 0 | 0 | 1 | |
+----------+----------+----------+----------+ |
| X | 0 | 1 | 0 |
+----------+----------+----------+----------+ NDMA value is either compatible
| 0 | 0 | 1 | 1 | to existing behavior or don't
+----------+----------+----------+----------+ care due to redundancy vs
| X | 1 | 0 | 0 | !_RUNNING/INVALID/ERROR
+----------+----------+----------+----------+
| X | 1 | 0 | 1 | |
+----------+----------+----------+----------+ |
| X | 1 | 1 | 0 | |
+----------+----------+----------+----------+ |
| X | 1 | 1 | 1 | v
+----------+----------+----------+----------+ ---
| 1 | 0 | 0 | 1 | ^
+----------+----------+----------+----------+ Desired new useful cases
| 1 | 0 | 1 | 1 | v
+----------+----------+----------+----------+ ---
Specifically, rows 1, 3, 5 with NDMA = 1 are valid states a user can
set which are simply redundant to the NDMA = 0 cases. Row 6 remains
invalid due to lack of support for pre-copy (_RESUMING | _RUNNING) and
therefore cannot be set by userspace. Rows 7 & 8 are error states and
cannot be set by userspace.
Like other bits, setting the bit should be effective at the completion
of writing device state. Therefore the device would need to flush any
outbound DMA queues before returning.
The question I was really trying to get to though is whether we have a
supportable interface without such an extension. There's currently
only an experimental version of vfio migration support for PCI devices
in QEMU (afaik), so it seems like we could make use of the bus-master
bit to fill this gap in QEMU currently, before we claim
non-experimental support, but this new device agnostic extension would
be required for non-PCI device support (and PCI support should adopt it
as available). Does that sound right? Thanks,
Alex
