On Thu, Oct 14, 2021 at 08:13:03AM +0000, Tian, Kevin wrote: > Based on above information my interpretation is that existing > DMA API manages coherency per device and It's not designed for > devices which are coherent in nature but also set PCI no-snoop > for selective traffic. Then the new DMA_ATTR_NO_SNOOP, once > set in dma_map, allows the driver to follow non-coherent > semantics even when the device itself is considered coherent. > > Does it capture the whole story correct? Yes. > > > What I don't really understand is why ARM, with an IOMMU that supports > > > PTE WB, has devices where dev_is_dma_coherent() == false ? > > > > Because no IOMMU in the world can help that fact that a periphal on the > > SOC is not part of the cache coherency protocol. > > but since DMA goes through IOMMU then isn't IOMMU the one who > should decide the final cache coherency? What would be the case > if the IOMMU sets WB while the peripheral doesn't want it? No. And IOMMU deal with address translation, it can't paper over a fact that there is no coherency possible.
