On 2021-09-30 14:35, Will Deacon wrote:
On Wed, Sep 22, 2021 at 01:46:55PM +0100, Fuad Tabba wrote:
From: Marc Zyngier <maz@xxxxxxxxxx>
+static bool kvm_hyp_handle_cp15(struct kvm_vcpu *vcpu, u64
*exit_code)
+{
+ if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
+ __vgic_v3_perform_cpuif_access(vcpu) == 1)
+ return true;
I think you're now calling this for the 64-bit CP15 access path, which
I
don't think is correct. Maybe have separate handlers for 32-bit v4
64-bit
accesses?
Good point. The saving grace is that there is no 32bit-capable CPU that
requires GICv3 trapping, nor any 64bit cp15 register in the GICv3
architecture apart form the SGI registers, which are always handled at
EL1.
So this code is largely academic!
Not providing a handler is the way to go for CP15-64.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
