On Tue, Aug 24, 2021 at 03:56:02PM +0800, Yang Weijiang wrote: Hi, Paolo and other maintainers, Do you have any comments on this patch series? Arch LBR is desired by customers on new Intel platforms, so we'd like to upstream these patches. Thanks a lot! > The Architectural Last Branch Records (LBRs) is published in the 319433-040 > release of Intel Architecture Instruction Set Extensions and Future Features > Programming Reference[0]. > > The main advantages of Arch LBR are [1]: > - Faster context switching due to XSAVES support and faster reset of > LBR MSRs via the new DEPTH MSR > - Faster LBR read for a non-PEBS event due to XSAVES support, which > lowers the overhead of the NMI handler. > - Linux kernel can support the LBR features without knowing the model > number of the current CPU. > > >From end user's point of view, the usage of Arch LBR is the same as > the Legacy LBR that has been merged in the mainline. > > Note, there's one limitations for current guest Arch LBR implementation: > Guest can only use the same LBR record depth as host, this is due to > the special behavior of MSR_ARCH_LBR_DEPTH: a) On write to the MSR, > it'll reset all Arch LBR recording MSRs to 0s. b) XRSTORS will reset all > recording MSRs to 0s if the saved depth mismatches MSR_ARCH_LBR_DEPTH. > > But this limitation won't impact guest perf tool usage. > > [0] https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference.html > [1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@xxxxxxxxxxxxxxx/ > > Previous version: > v7: https://lkml.kernel.org/kvm/1628235745-26566-1-git-send-email-weijiang.yang@xxxxxxxxx/ > > Changes in v8: > 1. Per Like's review feedback, changed corresponding patches. > 2. Refactored part of the code, i.e., arch lbr depth, control configuration, to make them more precise. > > > Like Xu (6): > perf/x86/intel: Fix the comment about guest LBR support on KVM > perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers > KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR > KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR > KVM: x86: Refine the matching and clearing logic for supported_xss > KVM: x86: Add XSAVE Support for Architectural LBR > > Sean Christopherson (1): > KVM: x86: Report XSS as an MSR to be saved if there are supported > features > > Yang Weijiang (8): > KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list > KVM: x86/pmu: Refactor code to support guest Arch LBR > KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS > KVM: x86/vmx: Check Arch LBR config when return perf capabilities > KVM: nVMX: Add necessary Arch LBR settings for nested VM > KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest > KVM: x86/vmx: Flip Arch LBREn bit on guest state change > KVM: x86/cpuid: Advise Arch LBR feature in CPUID > > arch/x86/events/intel/core.c | 3 +- > arch/x86/events/intel/lbr.c | 6 +- > arch/x86/include/asm/kvm_host.h | 4 + > arch/x86/include/asm/msr-index.h | 1 + > arch/x86/include/asm/vmx.h | 4 + > arch/x86/kvm/cpuid.c | 54 ++++++++++- > arch/x86/kvm/vmx/capabilities.h | 25 +++-- > arch/x86/kvm/vmx/nested.c | 6 +- > arch/x86/kvm/vmx/pmu_intel.c | 159 ++++++++++++++++++++++++++++--- > arch/x86/kvm/vmx/vmcs12.c | 1 + > arch/x86/kvm/vmx/vmcs12.h | 3 +- > arch/x86/kvm/vmx/vmx.c | 64 ++++++++++++- > arch/x86/kvm/x86.c | 24 ++++- > 13 files changed, 311 insertions(+), 43 deletions(-) > > -- > 2.25.1
