On Thu, Aug 19, 2021 at 10:11:09AM +0100, Marc Zyngier wrote:
> On Mon, 16 Aug 2021 01:12:13 +0100,
> Oliver Upton <oupton@xxxxxxxxxx> wrote:
> >
> > Allow userspace to access the guest's virtual counter-timer offset
> > through the ONE_REG interface. The value read or written is defined to
> > be an offset from the guest's physical counter-timer. Add some
> > documentation to clarify how a VMM should use this and the existing
> > CNTVCT_EL0.
> >
> > Signed-off-by: Oliver Upton <oupton@xxxxxxxxxx>
> > Reviewed-by: Andrew Jones <drjones@xxxxxxxxxx>
> > ---
> > Documentation/virt/kvm/api.rst | 10 ++++++++++
> > arch/arm64/include/uapi/asm/kvm.h | 1 +
> > arch/arm64/kvm/arch_timer.c | 23 +++++++++++++++++++++++
> > arch/arm64/kvm/guest.c | 6 +++++-
> > include/kvm/arm_arch_timer.h | 1 +
> > 5 files changed, 40 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
> > index dae68e68ca23..adb04046a752 100644
> > --- a/Documentation/virt/kvm/api.rst
> > +++ b/Documentation/virt/kvm/api.rst
> > @@ -2463,6 +2463,16 @@ arm64 system registers have the following id bit patterns::
> > derived from the register encoding for CNTV_CVAL_EL0. As this is
> > API, it must remain this way.
> >
> > +.. warning::
> > +
> > + The value of KVM_REG_ARM_TIMER_OFFSET is defined as an offset from
> > + the guest's view of the physical counter-timer.
> > +
> > + Userspace should use either KVM_REG_ARM_TIMER_OFFSET or
> > + KVM_REG_ARM_TIMER_CNT to pause and resume a guest's virtual
> > + counter-timer. Mixed use of these registers could result in an
> > + unpredictable guest counter value.
> > +
> > arm64 firmware pseudo-registers have the following bit pattern::
> >
> > 0x6030 0000 0014 <regno:16>
> > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
> > index b3edde68bc3e..949a31bc10f0 100644
> > --- a/arch/arm64/include/uapi/asm/kvm.h
> > +++ b/arch/arm64/include/uapi/asm/kvm.h
> > @@ -255,6 +255,7 @@ struct kvm_arm_copy_mte_tags {
> > #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
> > #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
> > #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
> > +#define KVM_REG_ARM_TIMER_OFFSET ARM64_SYS_REG(3, 4, 14, 0, 3)
> >
>
> Andrew, does this warrant an update to the selftest that checks for
> sysreg visibility?
Yup, until we do, the test will emit a warning with a suggestion to add
the new register to the list. It won't be a test FAIL, because adding new
registers doesn't break migration from older kernels, but we might as well
update the list sooner than later.
>
> I am also wondering how a VMM such as QEMU is going to deal with the
> above restriction, given the way it blindly saves/restores all the
> registers that KVM exposes, hence hitting that mixed-use that the
> documentation warns about...
You're right and I think it's a problem. While we can special case
registers in QEMU using a cpreg "level" so they won't get saved/restored
all the time, it doesn't help here since we won't be special casing
KVM_REG_ARM_TIMER_OFFSET in older QEMU. We need a way for the VMM to opt
in to using KVM_REG_ARM_TIMER_OFFSET, such as with a CAP we can enable.
Thanks,
drew
