On Mon, Aug 09, 2021 at 01:08:32PM +0800, Like Xu wrote:
> On 6/8/2021 3:42 pm, Yang Weijiang wrote:
> >Per ISA spec, need to clear the bit before inject #DB.
>
> Please paste the SDM statement accurately so that the reviewers
> can verify that the code is consistent with the documentation.
>
Thanks Like! Sure, will add the description in commit message.
> >
> >Signed-off-by: Yang Weijiang <weijiang.yang@xxxxxxxxx>
> >---
> > arch/x86/kvm/vmx/vmx.c | 21 +++++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> >diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> >index 70314cd93340..31b9c06c9b3b 100644
> >--- a/arch/x86/kvm/vmx/vmx.c
> >+++ b/arch/x86/kvm/vmx/vmx.c
> >@@ -1601,6 +1601,21 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
> > vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
> > }
> >+static void flip_arch_lbr_ctl(struct kvm_vcpu *vcpu, bool on)
> >+{
> >+ if (vcpu_to_pmu(vcpu)->event_count > 0 &&
>
> Ugh, this check seems ridiculous/funny to me.
Do you expect aditional bit-check for INTEL_PMC_IDX_FIXED_VLBR in
pmu->pmc_in_use?
>
> >+ kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) {
> >+ u64 lbr_ctl = vmcs_read64(GUEST_IA32_LBR_CTL);
> >+
> >+ if (on)
> >+ lbr_ctl |= 1ULL;
> >+ else
> >+ lbr_ctl &= ~1ULL;
> >+
> >+ vmcs_write64(GUEST_IA32_LBR_CTL, lbr_ctl);
> >+ }
> >+}
>
> ...
