On Fri, Aug 06, 2021 at 02:45:26PM +1000, David Gibson wrote: > Well, that's kind of what I'm doing. PCI currently has the notion of > "default" address space for a RID, but there's no guarantee that other > buses (or even future PCI extensions) will. The idea is that > "endpoint" means exactly the (RID, PASID) or (SID, SSID) or whatever > future variations are on that. This is already happening in this proposal, it is why I insisted that the driver facing API has to be very explicit. That API specifies exactly what the device silicon is doing. However, that is placed at the IOASID level. There is no reason to create endpoint objects that are 1:1 with IOASID objects, eg for PASID. We need to have clear software layers and responsibilities, I think this is where the VFIO container design has fallen behind. The device driver is responsible to delcare what TLPs the device it controls will issue The system layer is responsible to determine how those TLPs can be matched to IO page tables, if at all The IO page table layer is responsible to map the TLPs to physical memory. Each must stay in its box and we should not create objects that smush together, say, the device and system layers because it will only make a mess of the software design. Since the system layer doesn't have any concrete objects in our environment (which is based on devices and IO page tables) it has to exist as metadata attached to the other two objects. Jason
