On Fri, Jul 2, 2021 at 3:05 PM <isaku.yamahata@xxxxxxxxx> wrote:
> +/* Management class fields */
> +enum tdx_guest_management {
> + TD_VCPU_PEND_NMI = 11,
> +};
> +
> +/* @field is any of enum tdx_guest_management */
> +#define TDVPS_MANAGEMENT(field) BUILD_TDX_FIELD(32, (field))
I am a little confused with this. According to the spec, PEND_NMI has
a field code of 0x200000000000000B
I can understand that 0x20 is the class code and the PEND_NMI field code is 0xB.
On the other hand, for the LAST_EXIT_TSC the field code is 0xA00000000000000A.
Based on your code and the table in the spec, I can see that there is
an additional mask (1ULL<<63) for readonly fields.
Is this information correct and is this included in the spec? I tried
to find it but somehow I do not see it clearly defined.
> +#define TDX1_NR_TDCX_PAGES 4
> +#define TDX1_NR_TDVPX_PAGES 5
> +
> +#define TDX1_MAX_NR_CPUID_CONFIGS 6
Why is this just 6? I am looking at the CPUID table in the spec and
there are already more than 6 CPUID leaves there.
> +#define TDX1_MAX_NR_CMRS 32
> +#define TDX1_MAX_NR_TDMRS 64
> +#define TDX1_MAX_NR_RSVD_AREAS 16
> +#define TDX1_PAMT_ENTRY_SIZE 16
> +#define TDX1_EXTENDMR_CHUNKSIZE 256
I believe all of the defined variables above need to be enumerated
with TDH.SYS.INFO.
> +#define TDX_TDMR_ADDR_ALIGNMENT 512
Is TDX_TDMR_ADDR_ALIGNMENT used anywhere or is it just for completeness?
> +#define TDX_TDMR_INFO_ALIGNMENT 512
Why do we have alignment of 512, I am assuming to make it cache line
size aligned for efficiency?
> +#define TDX_TDSYSINFO_STRUCT_ALIGNEMNT 1024
typo: ALIGNEMNT -> ALIGNMENT
-Erdem
