On Tue, Jul 13, 2021 at 9:35 AM Sean Christopherson <seanjc@xxxxxxxxxx> wrote: > > Preserve CR0.CD and CR0.NW on INIT instead of forcing them to '1', as > defined by both Intel's SDM and AMD's APM. > > Note, current versions of Intel's SDM are very poorly written with > respect to INIT behavior. Table 9-1. "IA-32 and Intel 64 Processor > States Following Power-up, Reset, or INIT" quite clearly lists power-up, > RESET, _and_ INIT as setting CR0=60000010H, i.e. CD/NW=1. But the SDM > then attempts to qualify CD/NW behavior in a footnote: > > 2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits > are cleared. > > Presumably that footnote is only meant for INIT, as the RESET case and > especially the power-up case are rather non-sensical. Another footnote > all but confirms that: > > 6. Internal caches are invalid after power-up and RESET, but left > unchanged with an INIT. > > Bare metal testing shows that CD/NW are indeed preserved on INIT (someone > else can hack their BIOS to check RESET and power-up :-D). > > Reported-by: Reiji Watanabe <reijiw@xxxxxxxxxx> > Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx> Reviewed-by: Reiji Watanabe <reijiw@xxxxxxxxxx> Thank you for the fix and checking the CD/NW with the bare metal testing. Regards, Reiji
