On 7/2/2021 8:46 PM, Peter Zijlstra wrote:
On Tue, Jun 22, 2021 at 05:43:03PM +0800, Zhu Lingshan wrote:
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 22386c1a32b4..8bf494f8af3e 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3970,8 +3970,15 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
.guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
};
- /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
- arr[0].guest |= arr[*nr].guest;
+ if (arr[*nr].host) {
+ /* Disable guest PEBS if host PEBS is enabled. */
+ arr[*nr].guest = 0;
+ } else {
+ /* Disable guest PEBS for cross-mapped PEBS counters. */
+ arr[*nr].guest &= ~pmu->host_cross_mapped_mask;
+ /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
+ arr[0].guest |= arr[*nr].guest;
+ }
Not saying I disagree, but is there any way for the guest to figure out
why things aren't working? Is there like a guest log we can dump
something in?
Hi Peter,
We expect to handle these cases in the "slow path" series, try to
cross-map the counters.
Thanks!
+void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu)
+{
+ struct kvm_pmc *pmc = NULL;
+ int bit;
+
+ for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl,
+ X86_PMC_IDX_MAX) {
+ pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, bit);
+
+ if (!pmc || !pmc_speculative_in_use(pmc) ||
+ !pmc_is_enabled(pmc))
+ continue;
+
+ if (pmc->perf_event && (pmc->idx != pmc->perf_event->hw.idx))
+ pmu->host_cross_mapped_mask |=
+ BIT_ULL(pmc->perf_event->hw.idx);
{ } again.
+ }
+}
