Hi Will, On Thu, Jul 1, 2021 at 2:33 PM Will Deacon <will@xxxxxxxxxx> wrote: > > On Tue, Jun 15, 2021 at 02:39:44PM +0100, Fuad Tabba wrote: > > Add hardware configuration register bit definitions for HCR_EL2 > > and MDCR_EL2. Future patches toggle these hyp configuration > > register bits to trap on certain accesses. > > > > No functional change intended. > > > > Signed-off-by: Fuad Tabba <tabba@xxxxxxxxxx> > > --- > > arch/arm64/include/asm/kvm_arm.h | 21 +++++++++++++++++++++ > > 1 file changed, 21 insertions(+) > > > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > > index bee1ba6773fb..a78090071f1f 100644 > > --- a/arch/arm64/include/asm/kvm_arm.h > > +++ b/arch/arm64/include/asm/kvm_arm.h > > @@ -12,7 +12,11 @@ > > #include <asm/types.h> > > > > /* Hyp Configuration Register (HCR) bits */ > > +#define HCR_TID5 (UL(1) << 58) > > +#define HCR_DCT (UL(1) << 57) > > #define HCR_ATA (UL(1) << 56) > > +#define HCR_AMVOFFEN (UL(1) << 51) > > +#define HCR_FIEN (UL(1) << 47) > > #define HCR_FWB (UL(1) << 46) > > #define HCR_API (UL(1) << 41) > > #define HCR_APK (UL(1) << 40) > > @@ -55,6 +59,7 @@ > > #define HCR_PTW (UL(1) << 2) > > #define HCR_SWIO (UL(1) << 1) > > #define HCR_VM (UL(1) << 0) > > +#define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39)) > > > > /* > > * The bits we set in HCR: > > @@ -276,11 +281,21 @@ > > #define CPTR_EL2_TZ (1 << 8) > > #define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */ > > #define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1 > > +#define CPTR_NVHE_EL2_RES0 (GENMASK_ULL(63, 32) | \ > > + GENMASK_ULL(29, 21) | \ > > + GENMASK_ULL(19, 14) | \ > > + (UL(1) << 11)) > > > > /* Hyp Debug Configuration Register bits */ > > #define MDCR_EL2_E2TB_MASK (UL(0x3)) > > #define MDCR_EL2_E2TB_SHIFT (UL(24)) > > +#define MDCR_EL2_HPMFZS (UL(1) << 36) > > +#define MDCR_EL2_HPMFZO (UL(1) << 29) > > +#define MDCR_EL2_MTPME (UL(1) << 28) > > +#define MDCR_EL2_TDCC (UL(1) << 27) > > +#define MDCR_EL2_HCCD (UL(1) << 23) > > #define MDCR_EL2_TTRF (UL(1) << 19) > > +#define MDCR_EL2_HPMD (UL(1) << 17) > > #define MDCR_EL2_TPMS (UL(1) << 14) > > #define MDCR_EL2_E2PB_MASK (UL(0x3)) > > #define MDCR_EL2_E2PB_SHIFT (UL(12)) > > @@ -292,6 +307,12 @@ > > #define MDCR_EL2_TPM (UL(1) << 6) > > #define MDCR_EL2_TPMCR (UL(1) << 5) > > #define MDCR_EL2_HPMN_MASK (UL(0x1F)) > > +#define MDCR_EL2_RES0 (GENMASK_ULL(63, 37) | \ > > + GENMASK_ULL(35, 30) | \ > > + GENMASK_ULL(25, 24) | \ > > + GENMASK_ULL(22, 20) | \ > > + (UL(1) << 18) | \ > > + GENMASK_ULL(16, 15)) > > There's an inconsistent mix of ULL and UL here. Given we're on arm64, > maybe just use GENMASK() and BIT() for these RES0 regions? The reason I use GENMASK_ULL instead of GENMASK, and UL()<< instead of BIT is to remain consistent with the rest of this file. It would definitely be clearer here, as you point out. I'll fix it. > Anyway, the bit positions all look fine. You're missing HLP in bit 26, > but I guess that's not something you care about? I don't need that bit. I could add it for completeness, but there are a few others that aren't here either... Cheers, /fuad > Will
