On Wed, Jun 23, 2021 at 11:29:08AM -0700, Jim Mattson wrote: > On Mon, May 10, 2021 at 1:16 AM Like Xu <like.xu@xxxxxxxxxxxxxxx> wrote: > > > > Arch LBRs are enabled by setting MSR_ARCH_LBR_CTL.LBREn to 1. A new guest > > state field named "Guest IA32_LBR_CTL" is added to enhance guest LBR usage. > > When guest Arch LBR is enabled, a guest LBR event will be created like the > > model-specific LBR does. > > > > On processors that support Arch LBR, MSR_IA32_DEBUGCTLMSR[bit 0] has no > > meaning. It can be written to 0 or 1, but reads will always return 0. > > Like IA32_DEBUGCTL, IA32_ARCH_LBR_CTL msr is also reserved on INIT. > > > > Signed-off-by: Like Xu <like.xu@xxxxxxxxxxxxxxx> > > --- > > arch/x86/events/intel/lbr.c | 2 -- > > arch/x86/include/asm/msr-index.h | 1 + > > arch/x86/include/asm/vmx.h | 2 ++ > > arch/x86/kvm/vmx/pmu_intel.c | 31 ++++++++++++++++++++++++++----- > > arch/x86/kvm/vmx/vmx.c | 9 +++++++++ > > 5 files changed, 38 insertions(+), 7 deletions(-) > > > Same comments as on the previous patch. Your guard for ensuring that > the new VMCS fields exist can be spoofed by a malicious userspace, and > the new MSR has to be enumerated by KVM_GET_MSR_INDEX_LIST. OK, will modify the code, thanks!
